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MM74HCT164 8-Bit Serial-in/Parallel-out Shift Register
February 1984 Revised February 1999
MM74HCT164 8-Bit Serial-in/Parallel-out Shift Register
General Description
The MM74HCT164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low consumption of standard CMOS integrated circuits. It also offers speeds comparable to low power Schottky devices. This 8-bit shift register has gated serial inputs and CLEAR. Each register bit is a D-type master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A LOW at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A HIGH level on one input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the CLEAR input. The 74HCT logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.
Features
s Typical propagation delay: 20 ns s Low quiescent current: 40 A maximum (74HCT Series) s Low input current: 1 A maximum s Fanout of 10 LS-TTL loads s TTL input compatible
Ordering Code:
Order Number MM74HCT164M MM74HCT164SJ MM74HCT164N Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP) JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and SOP
Truth Table
Inputs Clear L H H H H Clock X L A X X H L X B X X H X L QA L QAO H L L Outputs QB L QBO QAn QAn QAn ... QH L QHO QGn QGn QGn
H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) = Transition from LOW-to-HIGH level. QAO, QBO, QHO = the level of QA, QB, or QH, respectively, before the indicated steady state input conditions were established. QAn, QGn = The level of QA or QG before the most recent transition of the clock; indicated a one-bit shift.
Top View
(c) 1999 Fairchild Semiconductor Corporation
DS005765.prf
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MM74HCT164
Logic Diagram
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MM74HCT164
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package Only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 25 mA 50 mA -65C to +150C
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT ) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) 500 ns
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
Max 5.5 VCC +85
Units V V C
4.5 0 -40
DC Electrical Characteristics
VCC = 5V 10% (unless otherwise specified) Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| = 20 A |IOUT| = 4.0 mA, VCC = 4.5V |IOUT| = 4.8 mA, VCC = 5.5V VOL Maximum LOW Level Voltage VIN = VIH or VIL |IOUT| = 20 A |IOUT| = 4.0 mA, VCC = 4.5V |IOUT| = 4.8 mA, VCC = 5.5V IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND IOUT = 0 A VIN = 2.4V or 0.4V (Note 4)
Note 4: This is measured per pin. All other inputs are held at VCC ground.
Conditions
TA = 25C Typ 2.0 0.8
TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 2.0 0.8 2.0 0.8
Units V V
VCC 4.2 5.2 0 0.2 0.2
VCC- 0.1 3.98 4.98 0.1 0.26 0.26 0.1
VCC- 0.1 3.84 4.84 0.1 0.33 0.33 1.0
VCC- 0.1 3.7 4.7 0.1 0.4 0.4 1.0
V V V V V V A
VIN = VCC or GND
8.0 1.0
80 1.3
160 1.5
A mA
3
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MM74HCT164
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX tPHL, tPLH tPHL, tPLH tREM tS tH tW Parameter Maximum Operating Frequency from Clock to Q Maximum Propagation Delay Clock to Q Maximum Propagation Delay from Clear to Q Minimum Removal Time, Clear to Clock Minimum Set Up Time Data to Clock Minimum Hold Time Clock to Data Minimum Pulse Width Clock, Preset or Clear 9 16 ns tS 20 ns 1.5 5 ns tH 20 ns 6 13 ns 3 6 ns 23 38 ns 50% Duty Cycle Clock 17 27 ns Conditions Typ 55 Guaranteed Limit 35 Units MHz
AC Electrical Characteristics
VCC = 5.0V, 10%, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay from Clock to Q tPHL tREM tS tH tW tr, tf Maximum Propagation Delay from Clear to Q Minimum Removal Time Clear to Clock Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Minimum Pulse Width Clock, or Clear Maximum Input Rise and Fall Time tTHL, tTLH Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance
Note 5: C PD determines the no load dynamic power consumption, PD=CPD VCC2 f+ICC VCC, and the no load dynamic current consumption, IS=CPD VCC f+ICC.
Conditions 50% Duty Cycle Clock
TA = 25C Typ 45 20 26 4 Max 30 30 41 8 15 5 18 500 15
TA = -40C to 85C TA = -55C to 125C Min Max 25 38 51 10 19 5 22 500 19 Min Max 22 45 61 14 23 5 27 500 22
Units MHz ns ns ns ns ns ns ns ns pF
tH 20 ns tS 20 ns
7 1.5 10
(per flip-flop)
160 5 10 10 10
pF
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MM74HCT164
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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MM74HCT164 8-Bit Serial-in/Parallel-out Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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